1. Field of the Invention
The present invention relates generally to computer system design. More specifically, the present invention relates to a method and an apparatus that facilitates logically partitioning different classes of translation lookaside buffer (TLB) entries within a single large caching structure.
2. Related Art
In order to support virtual addressing, modern computer systems typically include a translation lookaside buffer (TLB), which is typically structured as a small fully-associative cache that stores frequently used mappings from virtual addresses to physical addresses. By accessing the TLB, the computer system can quickly translate virtual addresses to physical addresses, without having to wait for page table entries (containing virtual-to-physical address translations) to be retrieved from main memory.
As computer systems begin to include multiple processors, some computer systems are beginning to support more-sophisticated forms of virtual addressing. For example, some multiprocessor systems support three types of addresses: (1) virtual addresses, which are associated with specific threads; (2) real addresses, which are associated with specific processors; and (3) physical addresses, which identify locations in physical memory (main memory).
To achieve acceptable performance in such systems, it is desirable to support TLB lookups for both real-to-physical address translations and virtual-to-physical address translations. This can be accomplished by providing separate caching structures (TLBs) for the different types of translations. However, providing separate caching structures for the different types of translations can consume a large amount of chip area because data paths must be routed to the separate structures.
This chip area problem can be alleviated by storing different classes of TLB entries within a single TLB. For example, a single TLB can be used to store entries for both real-to-physical address translations and virtual-to-physical address translations. However, this can cause performance problems, because if one class of TLB entries is accessed more frequently than the other class of TLB entries, the less frequently accessed class of TLB entries will tend to get evicted from the TLB. This will cause a high frequency of TLB misses (and resulting performance degradation) for the less frequently accessed class of TLB entries.
Hence, what is needed is a method and an apparatus for efficiently accessing multiple classes of TLB entries in a computer system without the problems described above.